The present invention relates to a semiconductor device including a plurality of memory modules having a low power consumption mode, which is suitable for use, for example, in a system-on-chip microcomputer including a plurality of memory modules as well as a central processing unit, an accelerator, etc.
When the semiconductor device is in the low power consumption mode, if the low power consumption mode is cancelled, supplying of electric power is restarted to a circuit to which no electric power is supplied in the low power consumption mode and a circuit in a non-operating state restarts operation. As a result, an inrush current and an undesirable increase in ground level can occur. This can cause electromigration to occur, which can in turn cause a failure to occur. Besides, a fluctuation in a logical threshold level can occur, which can cause an error to occur in operation. In particular, in a case where the memory modules installed in the semiconductor device have a large storage capacity, a large inrush current can occur when the lower power consumption state is cancelled for many memory modules. Thus there is a need for a technique to reduce an inrush current that occurs when the low power consumption mode is cancelled, and some techniques are disclosed in patent documents, typical examples of which are described below.
Japanese Unexamined Patent Publication No. 2007-164822 discloses a technique in which a plurality of semiconductor chips are coupled in a daisy chain form to each other using signal lines (bonding wires), and a power-on control signal is transmitted via the signal lines to thereby control timing of turning on electric power of the semiconductor chips such that the semiconductor chips are not turned on simultaneously but sequentially thereby preventing a high current peak from occurring during a turn-on operation.
Japanese Unexamined Patent Publication No. 2008-91030 discloses a technique in which a semiconductor integrated circuit device including a plurality of circuit blocks that are individually controlled in terms of turning-on/off and that are capable of individually executing commands is configured such that timing of activating electric power of one circuit block is controlled such that the activating is performed during a period in which a command is being executed by another circuit block thereby making it possible to prevent an occurrence of a high peak in current due to overlapping of timing of activating electric power among circuit blocks.
In terms of controlling the low power consumption mode, Japanese Unexamined Patent Publication No. 2007-173385 discloses a technique in which when an operation is brought in a resume standby mode to shut off electric power supply to peripheral circuits other than an SRAM memory array while maintaining information stored in the SRAM memory array, the ground level of the memory array is raised by about 0.3 V to reduce leakage currents.